View MT48LC4M32LFF5_4100080.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

128Mb: x16, x32 MOBILE SDRAM
SYNCHRONOUS DRAM
Features
* Temperature Compensated Self Refresh (TCSR) * Fully synchronous; all signals registered on positive edge of system clock * Internal pipelined operation; column address can be changed every clock cycle * Internal banks for hiding row access/precharge * Programmable burst lengths: 1, 2, 4, 8, or full page * Auto Precharge, includes CONCURRENT auto precharge, and Auto Refresh Modes * Self Refresh Mode; standard and low power * 64ms, 4,096-cycle refresh * LVTTL-compatible inputs and outputs * Low voltage power supply * Partial Array Self Refresh power-saving mode
OPTIONS MARKING LC G V
MT48G8M16LFFF, MT48G8M16LFF4, MT48LC8M16LFFF, MT48LC8M16LFF4, MT48V8M16LFF4, MT48V8M16LFFF MT48LC4M32LFFC, MT48LC4M32LFF5, MT48V4M32LFFC, MT48V4M32LFF5 For the latest data sheet, please refer to the Micron Web site: www.micron.com/dramds
Figure 1: Pin Assignment (Top View) 54-Ball FBGA
1 A B C D E F G H J
VSS
2
DQ15
3
VSSQ
4
5
DQ14
DQ13
VDDQ
DQ12
DQ11
DQ10
DQ9
UDQM
* VDD/VDDQ 3.3V/3.3V 3.0V/3.0V1 2.5V/2.5V - 1.8V * Configurations 8 Meg x 16 (2 Meg x 16 x 4 banks) 4 Meg x 32 (1 Meg x 32 x 4 banks) * Package/Ball out 54-ball FBGA (8mm x 9mm)2 54-ball FBGA (8mm x 9mm)2 Lead-Free 54-ball VFBGA (8mm x 8mm)2 54-ball VFBGA (8mm x 8mm)2 Lead-Free 90-ball FBGA (11mm x 13mm)3 90-ball FBGA (11mm x 13mm)3 Lead-Free 90-ball VFBGA (8mm x 13mm)3 90-ball VFBGA (8mm x 13mm)3 Lead-Free * Timing (Cycle Time) 8ns @ CL = 3 (125 MHz) 10ns @ CL = 3 (100 MHz) * Temperature Commercial (0C to +70C) Industrial (-40C to +85C) Extended (-25C to +75C)
w
w
w
.D
t a
8M16 4M32 FF BF F4 B4 FC BC F5 B5
S a
e h
NC/A12
t e
DQ8 NC A8 A7 VSS A5
CLK
U 4
VDDQ VSS CKE A9 A6 A4
VSSQ
.c
m o
6 7
VDDQ VSSQ VDDQ VSSQ VDD CAS# BA0 A0
8
9
VDD
DQ0
DQ2
DQ1
DQ4
DQ3
DQ6
DQ5
LDQM
DQ7
RAS#
WE#
A11
BA1
CS#
A1
A10
A3
A2
VDD
Top View (Ball Down)
8 Meg x 16 Configuration Refresh Count Row Addressing Bank Addressing Column Addressing 4K 4K (A0-A11) 4 (BA0, BA1) 512 (A0-A8)
4 Meg x 32 4K 4K (A0-A11) 4 (BA0, BA1) 256 (A0-A7)
2 Meg x 16 x 4 banks 1 Meg x 32 x 4 banks
Part Number Example:
Table 1:
-8 -10 None IT XT
MT48V8M16LFFF-8 Key Timing Parameters
ACCESS TIME CL=1* CL=2* CL=3*
tRCD
SPEED CLOCK GRADE FREQUENCY
NOTE:
1. Check with factory for configuration and availability. 2. x16 Only. 3. x32 Only.
-8 -10 -8 -10 -8 -10
125 MHz 100 MHz 100 MHz 83 MHz 50 MHz 40 MHz
- - - - 19ns 22ns
*CL = CAS (READ) latency
09005aef8071a76b MobileY95W_3V_1.fm - Rev. H 10/03 EN
1
w
w
w
.D
at
- - 8ns 8ns - -
Sh a
7ns 7ns - - - -
et e
20ns 20ns 20ns 20ns 20ns 20ns
4U
.
tRP
om c
20ns 20ns 20ns 20ns 20ns 20ns
(c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Temperature Compensated Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Command Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 NO Operation (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 LOAD mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 ACTIVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 AUTO REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 SELF REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 BANK/ROW ACTIVATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 CLOCK SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 BURST READ/SINGLE WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 CONCURRENT Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
09005aef8071a76b MobileY95W_3VTOC.fm - Rev. H 10/03 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
List of Figures
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Pin Assignment (Top View) 54-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 90-Ball FBGA Pin Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Functional Block Diagram 8 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Functional Block Diagram 4 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 READ to WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 WRITE to READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Initialize and Load Mode Register1,2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Power-down Mode1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 READ - Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Read - With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Single Read - Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Single Read - With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Alternating Bank Read Accesses1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Read - Full-page Burst1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Read - DQM Operation1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Write - Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Write - With Auto Precharge1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Single Write - Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Single Write - With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Alternating Bank Write Accesses1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Write - Full-page Burst1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Write - DQM Operation1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 54-Ball FBGA (8mm x 9mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 54-Ball VFBGA (8mm x 8mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 90-Ball FBGA (11mm x 13mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 90-Ball VFBGA (8mm x 13mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
List of Tables
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 128Mb SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Ball Descriptions: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Ball Descriptions: 90-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Truth Table-Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Truth Table - CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Truth Table - Current State Bank n, Command To Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Truth Table - CURRENT STATE BANK n, COMMAND TO BANK m. . . . . . . . . . . . . . . . . . . . . . . . . . . .34 DC Electrical Characteristics and Operating Conditions (LC Version). . . . . . . . . . . . . . . . . . . . . . . . . .36 DC Electrical Characteristics and Operating Conditions (G Version). . . . . . . . . . . . . . . . . . . . . . . . . . .36 DC Electrical Characteristics and Operating Conditions (V Version) . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .38 AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 IDD Specifications and Conditions (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 IDD7 Self Refresh Current Options (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 IDD Specifications And Conditions (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 IDD7 Self Refresh Current Options (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 2: 90-Ball FBGA Pin Assignment (Top View)
1 A
DQ26
2
3
4
5
6
7
8
9
DQ24
VSS
VDD
DQ23
DQ21
B
DQ28 VDDQ VSSQ VDDQ VSSQ DQ19
C
VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ
D
VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ
E
VDDQ DQ31 NC NC DQ16 VSSQ
F
VSS DQM3 A3 A2 DQM2 VDD
G
A4 A5 A6 A10 A0 A1
H
A7 A8 NC NC BA1 A11
J
CLK CKE A9 BA0 CS# RAS#
K
DQM1 NC NC CAS# WE# DQM0
L
VDDQ DQ8 VSS VDD DQ7 VSSQ
M
VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ
N
VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ
P
DQ11 VDDQ VSSQ VDDQ VSSQ DQ4
R
DQ13 DQ15 VSS VDD DQ0 DQ2
Ball and Array
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Table 2: 128Mb SDRAM Part Numbers
VDD/VDDQ 3.3V / 3.3V 3.0V / 3.0V 2.5V / 2.5V - 1.8V 3.3V / 3.3V 2.5V / 2.5V - 1.8V 3.3V / 3.3V 3.0V / 3.0V 2.5V / 2.5V - 1.8V 3.3V / 3.3V 2.5V / 2.5V - 1.8V ARCHITECTURE 8 Meg x 16 8 Meg x 16 8 Meg x 16 4 Meg x 32 4 Meg x 32 8 Meg x 16 8 Meg x 16 8 Meg x 16 4 Meg x 32 4 Meg x 32 PACKAGE 54-BALL FBGA 54-BALL FBGA 54-BALL FBGA 90-BALL FBGA 90-BALL FBGA 54-BALL VFBGA 54-BALL VFBGA 54-BALL VFBGA 90-BALL FBGA 90-BALL FBGA
PART NUMBER MT48LC8M16LFFF-xx MT48G8M16LFFF-xx MT48V8M16LFFF-xx MT48LC4M32LFFC-xx MT48V4M32LFFC-xx MT48LC8M16LFF4-xx MT48G8M16LFF4-xx MT48V8M16LFF4-xx MT48LC4M32LFF5-xx MT48V4M32LFF5-xx
General Description
The Micron(R) 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quadbank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16's 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Each of the x32's 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11(x16) or A0-A10(x32) select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless high-speed, random-access operation. The 128Mb SDRAM is designed to operate in 3.3V or 3.0V or 2.5V low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTLcompatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 3: Functional Block Diagram 8 Meg x 16 SDRAM
CKE CLK CS# WE# CAS# RAS# CONTROL LOGIC
BA1 0 0 1 1
BA0 0 1 0 1
Bank 0 1 2 3
COMMAND DECODE
BANK3 BANK2 BANK1
MODE REGISTER
REFRESH 12 COUNTER
12 12
ROWADDRESS MUX
12
BANK0 ROWADDRESS LATCH & DECODER
4096
BANK0 MEMORY ARRAY (4,096 x 512 x 16)
2
2
DQML, DQMH
SENSE AMPLIFIERS 16 4096
DATA OUTPUT REGISTER
2
A0-A11, BA0, BA1
14
ADDRESS REGISTER
2
BANK CONTROL LOGIC
I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 16 512 (x16) DATA INPUT REGISTER
16
DQ0DQ15
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH
9
9
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 4: Functional Block Diagram 4 Meg x 32 SDRAM
CKE CLK CS# WE# CAS# RAS# CONTROL LOGIC
BA1 0 0 1 1
BA0 0 1 0 1
Bank 0 1 2 3
COMMAND DECODE
BANK3 BANK2 BANK1 BANK0
MODE REGISTER
REFRESH 12 COUNTER
12 12
ROWADDRESS MUX
12
BANK0 ROWADDRESS LATCH & DECODER
4096
BANK0 MEMORY ARRAY (4,096 x 256 x 32)
4
4
DQM0- DQM3
SENSE AMPLIFIERS 32 4096
DATA OUTPUT REGISTER
2
A0-A11, BA0, BA1
14
ADDRESS REGISTER
2
BANK CONTROL LOGIC
I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 32 256 (x32) DATA INPUT REGISTER
32
DQ0- DQ31
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH
8
8
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Table 3:
F2
Ball Descriptions: 54-Ball VFBGA
SYMBOL CLK TYPE Input DESCRIPTION Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the command being entered. Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM corresponds to DQ0-DQ7, UDQM corresponds to DQ8-DQ15. LDQM and UDQM are considered same state when referenced as DQM. Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command Address Inputs: A0-A11 are sampled during the ACTIVE command (rowaddress A0-A11) and READ/WRITE command (column-address A0-A8; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data Input/Output: Data bus
54-BALL VFBGA
F3
CKE
Input
G9
CS#
Input
F7, F8, F9
CAS#, RAS#, WE# LDQM, UDQM
Input
E8, F1
Input
G7, G8
BA0, BA1
Input
H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2
A0-A11
Input
A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 E2, G1 A7, B3, C7, D3 A3, B7, C3, D7, A9, E7, J9 A1, E3, J1
DQ0-DQ15
I/O
NC
VDDQ VSSQ VDD VSS
- Supply Supply Supply Supply
No Connect: These pins should be left unconnected. G1 is a no connect for this part but may be used as A12 in future designs. DQ Power: Isolated DQ power on the die to improve noise immunity. DQ Ground: Isolated DQ power on the die to improve noise immunity. Power Supply: Voltage dependant on option. Ground.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Table 4:
J1
Ball Descriptions: 90-Ball VFBGA
SYMBOL CLK TYPE Input DESCRIPTION Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. DQM0 corresponds to DQ0-DQ7, DQM1 corresponds to DQ8-DQ15, DQM2 corresponds to DQ16-DQ23 and DQM3 corresponds to DQ24-DQ31. DQM0-3 are considered same state when referenced as DQM. Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command Address Inputs: A0-A11 are sampled during the ACTIVE command (rowaddress A0-A11) and READ/WRITE command (column-address A0-A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data Input/Output: Data bus
90-BALL FBGA
J2
CKE
Input
J8
CS#
Input
J9, K7, K8 K9, K1, F8, F2
RAS#, CAS#, WE# DQM0-3
Input Input
J7, H8
BA0, BA1
Input
G8, G9, F7, F3, G1, G2, G3, H1, H2, J3, G7, H9
A0-A11
Input
R8, N7, R9, N8, P9, M8, M7, L8, L2, M3, M2, P1, N2, R1, N3, R2, E8, D7, D8, B9, C8, A9, C7, A8, A2, C3, A1, C2, B1, D2, D3, E2 E3, E7, H3, H7, K2, K3 B2, B7, C9, D9, E1, L1, M9, N9, P2, P7 B8, B3, C1, D1, E9, L9, M1, N1, P3, P8 A7, F9, L7, R7 A3, F1, L3, R3
DQ0-DQ31
I/O
NC
VDDQ VSSQ VDD VSS
No Connect: These pins should be left unconnected. H7 is a no connect for this part but may be used as A12 in future designs. Supply DQ Power: Isolated DQ power on the die to improve noise immunity. Supply DQ Ground: Isolated DQ power on the die to improve noise immunity. Supply Power Supply: Voltage dependant on option. Supply Ground.
-
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Functional Description
In general, the 128Mb SDRAMs (2 Meg x16 x 4 banks and 1 Meg x 32 x 4 banks) are quad-bank DRAMs that operate at 3.3V or 2.5V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16's 33,554,432bit banks is organized as 4,096 rows by 512 columns by 16 bits. Each of the x32's 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A11 select the row). The address bits (x16: A0-A8; x32: A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
Register Definition Mode Register
In order to achieve low power consumption, there are two mode registers in the Mobile component, Mode Register and Extended Mode Register. For this section, Mode Register is referred to. Extended Mode register is discussed on 14. The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 5. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode Register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9, M10, and M11 should be set to zero. M12 and M13 should be set to zero to prevent extended mode register. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to Vdd and VddQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100s delay prior to issuing any command other than a COMMAND INHIBIT or NOP Starting at some point during . this 100s period and continuing at least through the end of this period, Command Inhibit or NOP commands should be applied. Once the 100s delay has been satisfied with at least one Command Inhibit or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO refresh cycles must be performed. After the AUTO refresh cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command.
Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 5. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A8 (x16) or A1-A7 (x32) when the burst length is set to two; by A2-A8 (x16) or A2-A7 (x32) when the burst length is set to four; and by A3-A8 (x16) or A3A7 (x32) when the burst length is set to eight. The
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
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128Mb: x16, x32 MOBILE SDRAM
remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Fullpage bursts wrap within the page if the boundary is reached.
Table 5:
Burst Definition
ORDER OF ACCESSES WITHIN A BURST
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.
BURST LENGTH 2
STARTING COLUMN ADDRESS A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 n = A0-A11/ 9/8 (location 0-y)
TYPE = SEQUENTIAL 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn + 4... ...Cn - 1, Cn...
TYPE = INTERLEAVED 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported
4
Figure 5: Mode Register Definition
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
M13 M12 M11 M10 M9 M8 13 LMR 12 11 10 9 8
M7 M6 M5 M4 7 6 5 4
M3 M2 M1 M0 3 2 1 0 Mode Register (Mx)
Reserved* WB Op Mode
CAS Latency
BT
Burst Length
8
*Should program M11 and M10 = "0, 0" to ensure compatibility with future devices.
Burst Length M2 M1 M0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved
Full Page (y)
M3 0 1
Burst Type Sequential Interleaved
M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved
M8 0 -
M7 0 -
M6-M0 Defined -
Operating Mode Standard Operation All other states reserved
M9 0 1
Write Burst Mode Programmed Burst Length Single Location Access
M13 0 -
M12 0 -
Load Mode Register Program Mode Register All other states reserved
NOTE: 1. For full-page accesses: y = 512 (x16), y = 256 (x32). 2. For a burst length of two, A1-A8 (x16) or A1-A7 (x32) select the block-of-two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A8 (x16) or A2-A7 (x32) select the block-of-four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A8 (x16) or A3-A7 (x32) select the block-of-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A8 (x16) or A0-A7 (x32) select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A8 (x16) or A0-A7 (x32) select the unique column to be accessed, and mode register bit M3 is ignored.
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CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two, or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 6. Table 6 indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both read and write bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Extended Mode Register The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are special features of the Mobile device. They include Temperature Compensated Self Refresh (TCSR) Control, and Partial Array Self Refresh (PASR).
Table 6:
CAS Latency
ALLOWABLE OPERATING FREQUENCY (MHZ)
Figure 6: CAS Latency
T0 CLK COMMAND T1 T2
SPEED -8 - 10
CAS CAS LATENCY = 1 LATENCY = 2 50 40 100 83
CAS LATENCY = 3 125 100
READ tLZ
NOP tOH DOUT
Figure 7: Extended Mode Register
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DQ tAC CAS Latency = 1
Address Bus
M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 13 12 11 10 1 0 9 8 7 6 5 4 TCSR 3 2 1 0 All must be set to "0" PASR Extended Mode Register (Ex)
T0 CLK COMMAND
T1
T2
T3
READ
NOP tLZ
NOP tOH DOUT
A4 1 0 0 1
A3 Maximum Case Temp 1 0 1 0 85C 70C 45C
15C
DQ tAC CAS Latency = 2
T0 CLK COMMAND
T1
T2
T3
T4
A2 0
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Self Refresh Coverage Four Banks Two Banks (Bank 0,1) One Bank (Bank 0) RFU RFU RFU RFU RFU
READ
NOP
NOP tLZ
NOP tOH DOUT
0 0 0 1 1
DQ tAC CAS Latency = 3
1
DON'T CARE
1
UNDEFINED
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The Extended Mode Register is programmed via the Mode Register Set command (BA1=1,BA0=0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be programmed with M5 through M11 set to "0". The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. The Extended Mode Register must be programmed in order to ensure proper operation. Temperature Compensated Self Refresh Temperature Compensated Self Refresh (TCSR) allows the controller to program the Refresh interval during SELF REFRESH mode, according to the case temperature of the Mobile device. This allows great power savings during SELF REFRESH during most operating temperature ranges. Only during extreme temperatures would the controller have to select a TCSR level that will guarantee data during SELF REFRESH. Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range expected. Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. Setting M4 and M3, allow the DRAM to accommodate more specific temperature regions during SELF REFRESH. There are four temperature settings, which will vary the SELF REFRESH current according to the selected temperature. This selectable refresh rate will save power when the DRAM is operating at normal temperatures. Partial Array Self Refresh For further power savings during SELF REFRESH, the Partial Array Self Refresh (PASR) feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. The refresh options are all banks (banks 0, 1, 2, and 3); two banks (banks 0 and 1); and one bank (bank 0). WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks in PASR will be refreshed during SELF REFRESH. It's important to note that data in banks 2 and 3 will be lost when the two bank option is used. Data will be lost in banks 1, 2, and 3 when the one bank option is used.
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128Mb: x16, x32 MOBILE SDRAM
Commands
Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following the Operation section; these tables provide current state/next state information.
Table 7:
(Note: 1)
Truth Table-Commands and DQM Operation
CS# H L L L L L L L L - - RAS# CAS# WE# X H L H H H L L L - - X H H L L H H L L - - X H H H L L L H L - - DQM X X X L/H
8
NAME (FUNCTION) COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z
NOTE:
ADDR X X Bank/Row Bank/Col Bank/Col X Code X Op-Code - -
DQS X X X X Valid Active X X X Active High-Z
NOTES
3 4 4 5 6, 7 2 8 8
L/H8 X X X X L H
1. 2. 3. 4. 5. 6. 7. 8.
CKE is HIGH for all commands shown except SELF REFRESH. A0-A10 define the op-code written to the mode register. A0-A11 provide row address, and BA0, BA1 determine which bank is made active. A0-A8 (x16) or A0-A7 (x32) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't Care." This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls DQ0-7, DQM1 controls DQ8-15, DQM2 controls DQ16-23, and DQM3 controls DQ24-31.
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Command Inhibit The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO Operation (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD mode register The mode register is loaded via inputs A0-A11. Refer to "Mode Register" on page 11. The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a precharge command is issued to that bank. A precharge command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 (x16) or A0-A7 (x32) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 (x16) or A0-A7 (x32) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Auto Precharge Auto precharge is a feature which performs the same individual-bank precharge function described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet. 16
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BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command as shown in the operation section. The addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The 128Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (tREF), regardless of width option. Providing a distributed AUTO REFRESH command every 15.625s will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms. SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become "Don't Care" with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh mode for a minimum period equal to t RAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 15.625s or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter.
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Operation
BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (seeFigure 8). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 9, which covers any case where 2 < t RCD (MIN)/tCK 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by t RRD.
Figure 8: Activating a Specific Row in a Specific Bank
CLK CKE CS# HIGH
RAS#
CAS#
WE#
A0-A10, A11
ROW ADDRESS
BA0, BA1
BANK ADDRESS
DON'T CARE
Figure 9: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3
T0 CLK T1 T2 T3 T4
COMMAND
ACTIVE
NOP
NOP
READ or WRITE
tRCD
DON'T CARE
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128Mb: x16, x32 MOBILE SDRAM
READs
READ bursts are initiated with a READ command, as shown in Figure 10. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 11 shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go HighZ. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixedlength READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one.
Figure 10: READ Command
CLK CKE CS# HIGH
CLK COMMAND
Figure 11: CAS Latency
T0 T1 T2
READ tLZ
NOP tOH DOUT
DQ tAC CAS Latency = 1
RAS#
T0
T1
T2
T3
CAS#
CLK COMMAND
WE#
READ
NOP tLZ
NOP tOH DOUT
DQ
x16: A0-A8 x32: A0-A7 A9, A11
COLUMN ADDRESS
tAC CAS Latency = 2
ENABLE AUTO PRECHARGE
T0 CLK
T1
T2
T3
T4
A10
DISABLE AUTO PRECHARGE
COMMAND
READ
NOP
NOP tLZ
NOP tOH DOUT
BA0,1
BANK ADDRESS
DQ
DON'T CARE
tAC CAS Latency = 3 DON'T CARE UNDEFINED
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128Mb: x16, x32 MOBILE SDRAM
This is shown in Figure 11 for CAS latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 12, or each subsequent READ may be performed to a different bank.
Figure 12: Consecutive READ Bursts
T0 CLK T1 T2 T3 T4 T5
COMMAND
READ
NOP
NOP
NOP
READ X = 0 cycles
NOP
ADDRESS
BANK, COL n
BANK, COL b
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b
CAS Latency = 1
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
X = 1 cycle
ADDRESS
BANK, COL n
BANK, COL b
DQ
CAS Latency = 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b
T0 CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
X = 2 cycles
ADDRESS
BANK, COL n
BANK, COL b
DQ
CAS Latency = 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b
NOTE: Each READ command may be to either bank. DQM is LOW. TRANSITIONING DATA DON'T CARE
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128Mb: x16, x32 MOBILE SDRAM
Figure 13: Random READ Accesses
T0 CLK T1 T2 T3 T4
COMMAND
READ
READ
READ
READ
NOP
ADDRESS
BANK, COL n
BANK, COL a
BANK, COL x
BANK, COL m
DQ
CAS Latency = 1
DOUT n
DOUT a
DOUT x
DOUT m
T0 CLK
T1
T2
T3
T4
T5
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL a
BANK, COL x
BANK, COL m
DQ
CAS Latency = 2
DOUT n
DOUT a
DOUT x
DOUT m
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL a
BANK, COL x
BANK, COL m
DQ
CAS Latency = 3
DOUT n
DOUT a
DOUT x
DOUT m
NOTE: Each READ command may be to either bank. DQM is LOW. TRANSITIONING DATA DON'T CARE
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128Mb: x16, x32 MOBILE SDRAM
Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixedlength READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a singlecycle delay should occur between the last read data and the WRITE command. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 14 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 15 shows the case where the additional NOP is needed.
Figure 15: READ to WRITE with Extra Clock Cycle
T0 CLK DQM T1 T2 T3 T4 T5
Figure 14: READ to WRITE
T0 CLK DQM T1 T2 T3 T4
COMMAND ADDRESS
READ
NOP
NOP
NOP
NOP
WRITE
BANK, COL n
BANK, COL b
tHZ DQ
DOUT n DIN b
tDS
COMMAND ADDRESS
READ
NOP
NOP
NOP
WRITE
TRANSITIONING DATA NOTE:
DON'T CARE
BANK, COL n
BANK, COL b
A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank.
tCK tHZ DQ
DOUT n DIN b
tDS TRANSITIONING DATA NOTE: DON'T CARE
A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required.
The DQM input is used to avoid I/O contention, as shown in Figure 14 and Figure 15. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 15, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 16 for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
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128Mb: x16, x32 MOBILE SDRAM
Figure 16: READ to PRECHARGE
T0 CLK
t RP
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
PRECHARGE X = 0 cycles
NOP
NOP
ACTIVE
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
DQ
CAS Latency = 1
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
T0 CLK
T1
T2
T3
T4
T5
T6
T7
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE X = 1 cycle
NOP
NOP
ACTIVE
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
DQ
CAS Latency = 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
T0 CLK
T1
T2
T3
T4
T5
T6
T7
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
DQ
CAS Latency = 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
NOTE: DQM is LOW.
TRANSITIONING DATA
DON'T CARE
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128Mb: x16, x32 MOBILE SDRAM
Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 17 for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst.
Figure 17: Terminating a READ Burst
T0 CLK T1 T2 T3 T4 T5 T6
COMMAND
READ
NOP
NOP
NOP
BURST TERMINATE X = 0 cycles
NOP
NOP
ADDRESS
BANK, COL n
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency = 1
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
NOP
NOP
NOP
BURST TERMINATE X = 1 cycle
NOP
NOP
ADDRESS
BANK, COL n
DQ
CAS Latency = 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
T0 CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
BURST TERMINATE
NOP
NOP
NOP
X = 2 cycles
ADDRESS
BANK, COL n
DQ
CAS Latency = 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
NOTE: DQM is LOW.
TRANSITIONING DATA
DON'T CARE
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128Mb: x16, x32 MOBILE SDRAM
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 18. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 19). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixedlength WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 19. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 20, or each subsequent WRITE may be performed to a different bank.
Figure 19: WRITE Burst
T0 CLK T1 T2 T3
Figure 18: WRITE Command
CLK CKE HIGH
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS CS# DQ RAS# NOTE: CAS#
BANK, COL n
DIN n
DIN n+1
Burst length = 2. DQM is LOW. TRANSITIONING DATA DON'T CARE
WE#
Figure 20: WRITE to WRITE
T0 T1 T2
COLUMN ADDRESS
x16: A0-A8 x32: A0-A7 A9, A11
CLK
COMMAND
ENABLE AUTO PRECHARGE
WRITE
NOP
WRITE
A10
DISABLE AUTO PRECHARGE
ADDRESS
BANK, COL n
BANK, COL b
DQ BA0,1
BANK ADDRESS
DIN n
DIN n+1
DIN b
NOTE: VALID ADDRESS DON'T CARE
DQM is LOW. Each WRITE command may be to any bank. DON'T CARE
TRANSITIONING DATA
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Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixedlength WRITE burst may be immediately followed by a READ command. Once the READ command is registered, the data inputs will be ignored, and writes will not be executed. An example is shown in Figure 22. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued t WR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR of at least one clock plus time, regardless of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 23. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Figure 21: Random WRITE Cycles
T0 T1 T2 T3
Figure 23: WRITE to PRECHARGE
T0 CLK
tWR@ tCK 15ns
T1
T2
T3
T4
T5
T6
CLK
COMMAND
WRITE
WRITE
WRITE
WRITE
DQM
t RP
ADDRESS
BANK, COL n
BANK, COL a
BANK, COL x
BANK, COL m
COMMAND
WRITE
NOP
PRECHARGE
NOP
NOP
ACTIVE
NOP
DQ NOTE:
DIN n
DIN a
DIN x
DIN m
ADDRESS
BANK a, COL n
t WR
BANK (a or all)
BANK a, ROW
Each WRITE command may be to any bank. DQM is LOW.
TRANSITIONING DATA DON'T CARE
DQ
DIN n
DIN n+1
tWR@ tCK < 15ns
Figure 22: WRITE to READ
T0 CLK T1 T2 T3 T4 T5
DQM
t RP
COMMAND ADDRESS
WRITE
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
BANK a, COL n
t WR
BANK (a or all)
BANK a, ROW
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
DQ
DIN n
DIN n+1
ADDRESS
BANK, COL n
BANK, COL b
NOTE:
DOUT b DOUT b+1
DQM could remain LOW in this example if the WRITE burst is a fixed length of two. TRANSITIONING DATA DON'T CARE
DQ NOTE:
DIN n
DIN n+1
The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW. CAS latency = 2 for illustration. TRANSITIONING DATA DON'T CARE
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Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 24, where data n is the last desired data element of a longer burst. PRECHARGE The PRECHARGE command (see Figure 25) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. POWER-DOWN Power-down occurs if CKE is registered low coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). See Figure 26.
Figure 24: Terminating a WRITE Burst
T0 CLK T1 T2
COMMAND
WRITE
BURST TERMINATE
NEXT COMMAND
ADDRESS
BANK, COL n
(ADDRESS)
DQ
DIN n
(DATA)
NOTE:
DQMs are LOW. DON'T CARE
TRANSITIONING DATA
Figure 25: PRECHARGE Command
CLK CKE CS# HIGH
Figure 26: Power-Down
CLK tCKS CKE
(( )) (( ))
RAS#
> tCKS
CAS#
COMMAND
NOP
(( ))
(( )) (( ))
NOP
ACTIVE
WE#
All banks idle Input buffers gated off Enter power-down mode. Exit power-down mode.
tRCD tRAS tRC DON'T CARE
A0-A9
All Banks
A10
Bank Selected
BA0,1
BANK ADDRESS
VALID ADDRESS
DON'T CARE
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CLOCK SUSPEND The clock suspend mode occurs when a column access/burst is in progress and CKE is registered low. In the clock suspend mode, the internal clock is deactivated, "freezing" the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figure 27 and Figure 28.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0).
Figure 27: Clock Suspend During WRITE Burst
T0 CLK T1 T2 T3 T4 T5
Figure 28: Clock Suspend During READ Burst
T0 CLK T1 T2 T3 T4 T5 T6
CKE
CKE
INTERNAL CLOCK
INTERNAL CLOCK
NOP WRITE NOP NOP
COMMAND
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
ADDRESS
BANK, COL n
ADDRESS
BANK, COL n
DIN
DIN n
DIN n+1
DIN n+2
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
TRANSITIONING DATA
DON'T CARE
TRANSITIONING DATA
DON'T CARE
NOTE: For this example, burst length = 4 or greater, and DM is LOW.
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and DQM is LOW.
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CONCURRENT Auto Precharge An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports Concurrent Auto precharge. Micron SDRAMs support Concurrent Auto precharge. Four cases where Concurrent Auto precharge occurs are defined below. READ with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CAS latency later. The precharge to bank n will begin when the READ to bank m is registered (Figure 29). 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The precharge to bank n will begin when the WRITE to bank m is registered (Figure 30).
Figure 29: READ With Auto Precharge Interrupted by a READ
T0 CLK
READ - AP BANK n READ - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
READ with Burst of 4
Interrupt Burst, Precharge t RP - BANK n
Idle tRP - BANK m Precharge
Internal States
BANK m
Page Active
READ with Burst of 4
ADDRESS DQ
BANK n, COL a
BANK m, COL d DOUT a DOUT a+1 DOUT d DOUT d+1
CAS Latency = 3 (BANK n) CAS Latency = 3 (BANK m)
NOTE: DQM is LOW.
TRANSITIONING DATA
DON'T CARE
Figure 30: READ With Auto Precharge Interrupted by a WRITE
T0 CLK
READ - AP BANK n Page Active WRITE - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
READ with Burst of 4
Interrupt Burst, Precharge tRP - BANK n
Idle t WR - BANK m Write-Back
Internal States
BANK m
BANK n, COL a
Page Active
WRITE with Burst of 4
ADDRESS 1 DQM DQ
BANK m, COL d
DOUT a CAS Latency = 3 (BANK n)
DIN d
DIN d+1
DIN d+2
DIN d+3
NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4. TRANSITIONING DATA DON'T CARE
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128Mb: x16, x32 MOBILE SDRAM
WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The precharge to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 31). 4. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (Figure 32).
Figure 31: WRITE With Auto Precharge Interrupted by a READ
T0 CLK
WRITE - AP BANK n READ - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back tWR - BANK n
Precharge tRP - BANK n tRP - BANK m
Internal States
BANK m
Page Active
READ with Burst of 4
ADDRESS DQ
BANK n, COL a DIN a DIN a+1
BANK m, COL d DOUT d CAS Latency = 3 (BANK m) DOUT d+1
NOTE: 1. DQM is LOW. TRANSITIONING DATA DON'T CARE
Figure 32: WRITE With Auto Precharge Interrupted by a WRITE
T0 CLK
WRITE - AP BANK n WRITE - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back tWR - BANK n
Precharge tRP - BANK n t WR - BANK m Write-Back
Internal States
BANK m
Page Active
WRITE with Burst of 4
ADDRESS DQ NOTE: 1. DQM is LOW.
BANK n, COL a DIN a DIN a+1 DIN a+2
BANK m, COL d DIN d DIN d+1 DIN d+2 DIN d+3
TRANSITIONING DATA
DON'T CARE
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128Mb: x16, x32 MOBILE SDRAM
Table 8:
(Notes: 1-4) CKEn-1 L CKEn L CURRENT STATE Power-Down Self Refresh Clock Suspend Power-Down Self Refresh Clock Suspend All Banks Idle All Banks Idle Reading or Writing COMMANDn X X X COMMAND INHIBIT or NOP COMMAND INHIBIT or NOP X COMMAND INHIBIT or NOP AUTO REFRESH VALID See Truth Table 3 ACTIONn Maintain Power-Down Maintain Self Refresh Maintain Clock Suspend Exit Power-Down Exit Self Refresh Exit Clock Suspend Power-Down Entry Self Refresh Entry Clock Suspend Entry NOTES
Truth Table - CKE
L
H
5 6 7
H
L
H
NOTE:
H
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state of the SDRAM immediately prior to clock edge n. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. All states and sequences not shown are illegal or reserved. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1.
1. 2. 3. 4. 5.
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Table 9:
CURRENT STATE Any Idle
Truth Table - Current State Bank n, Command To Bank n
CS# RAS# CAS# WE# COMMAND (ACTION) H X X X COMMAND INHIBIT (NOP/Continue previous operation) L H H H NO OPERATION (NOP/Continue previous operation) L L H H ACTIVE (Select and activate row) L L L H AUTO REFRESH L L L L LOAD MODE REGISTER L L H L PRECHARGE L H L H READ (Select column and start READ burst) L H L L WRITE (Select column and start WRITE burst) L L H L PRECHARGE (Deactivate row in bank or banks) L H L H READ (Select column and start new READ burst) L H L L WRITE (Select column and start WRITE burst) L L H L PRECHARGE (Truncate READ burst, start PRECHARGE) L H H L BURST TERMINATE L H L H READ (Select column and start READ burst) L H L L WRITE (Select column and start new WRITE burst) L L H L PRECHARGE (Truncate WRITE burst, start PRECHARGE) L H H L BURST TERMINATE NOTES
Notes: 1-6; notes appear below table
Row Active
Read (Auto Precharge Disabled) Write (Auto Precharge Disabled)
NOTE:
7 7 11 10 10 8 10 10 8 9 10 10 8 9
1. This table applies when CKEn-1 was HIGH and CKEnis HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle:The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
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128Mb: x16, x32 MOBILE SDRAM
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. 10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank.
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128Mb: x16, x32 MOBILE SDRAM
Table 10: Truth Table - CURRENT STATE BANK n, COMMAND TO BANK m
Notes: 1-6; notes appear below and on next page CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) Any Idle Row Activating, Active, or Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) Read (With Auto Precharge) Write (With Auto Precharge)
NOTE:
NOTES
H L X L L L L L L L L L L L L L L L L L L L L
X H X L H H L L H H L L H H L L H H L L H H L
X H X H L L H H L L H H L L H H L L H H L L H
X H X H H L L H H L L H H L L H H L L H H L L
COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) Any Command Otherwise Allowed to Bank m ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE
7 7
7, 10 7, 11 9 7, 12 7, 13 9 7, 8, 14 7, 8, 15 9 7, 8, 16 7, 8, 17 9
1. This table applies when CKEn-1 was HIGH and CKEnis HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
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8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m's burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 12). 11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (Figure 14 and Figure 15). DQM should be used one clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 22), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank will interrupt the WRITE on bank n when registered (Figure 20). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 29). 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 30). 16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in registered one clock prior to the READ to bank m (Figure 31). 17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m (Figure 32).
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Absolute Maximum Ratings
Voltage on VDD/VDDQ Supply Relative to VSS(LC, G devices) . . . . . . . .-1V to +4.6V Relative to VSS(V devices) . . . . . . . . . . . 0.5V to +3.6V Voltage on Inputs, NC or I/O Pins Relative to VSS(LC, G devices) . . . . . . . .-1V to +4.6V Relative to VSS(V devices) . . . . . . . . . . -0.5V to +3.6V Operating Temperature TA (Commercial) . . . . . . . . . . . . . . . . . . . 0C to +70C TA (Industrial) . . . . . . . . . . . . . . . . . . . -40C to +85C TA (Extended) . . . . . . . . . . . . . . . . . . . -25C to +75C Storage Temperature (plastic) . . . . -55C to +150C Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 11: DC Electrical Characteristics and Operating Conditions (LC Version)
Notes: 1, 6; notes appear on page 42; VDD= +3.3V 0.3V, VDDQ = +3.3V 0.3V PARAMETER/CONDITION Supply Voltage I/O Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Data Output High Voltage: Logic 1; All inputs Data Output LOW Voltage: Logic 0; All inputs Input Leakage Current: Any Input 0V VIN VDD (All other pins not under test = 0V) Output Leakage Current: DQs are disabled; 0V VOUT VDDQ SYMBOL VDD VDDQ VIH VIL VOH VOL II IOZ MIN 3 3 2 -0.3 2.4 - -5 -5 MAX 3.6 3.6 VDD + 0.3 0.8 - 0.4 5 5 UNITS V V V V V V A A NOTES
22 22
Table 12: DC Electrical Characteristics and Operating Conditions (G Version)
Notes: 1, 6; notes appear on page 42; VDD = +3.0V 0.3V, VDDQ = +3.0V 0.3V PARAMETER/CONDITION Supply Voltage I/O Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Data Output High Voltage: Logic 1; All inputs Data Output LOW Voltage: Logic 0; All inputs Input Leakage Current: Any Input 0V VIN VDD (All other pins not under test = 0V) Output Leakage Current: DQs are disabled; 0V VOUT VDDQ SYMBOL VDD VDDQ VIH VIL VOH VOL II IOZ MIN 2.7 2.7 2 -0.3 2.4 - -5 -5 MAX 3.3 3.3 VDD + 0.3 0.8 - 0.4 5 5 UNITS V V V V V V A A NOTES
22 22
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Table 13: DC Electrical Characteristics and Operating Conditions (V Version)
Notes: 1, 6; notes appear on page 42; VDD = 2.5 0.2V, VDDQ = +2.5V 0.2V or +1.8V 0.15V PARAMETER/CONDITION Supply Voltage I/O Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Data Output High Voltage: Logic 1; All inputs Data Output Low Voltage: Logic 0; All inputs Input Leakage Current: Any input 0V VIN VDD (All other pins not under test = 0V) Output Leakage Current: DQs are disabled; 0V VOUT VDDQ SYMBOL VDD VDDQ VIH VIL VOH VOL II IOZ MIN 2.3 1.65 1.25 -0.3 VDDQ - 0.2 - -2 -5 MAX 2.7 2.7 VDD + 0.3 +0.55 - 0.2 2 5 UNITS V V V V V V A A NOTES
22 22
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Table 14: Electrical Characteristics and Recommended AC Operating Conditions
Notes: 5, 6, 7, 8, 9, 11; notes appear on page 42 AC CHARACTERISTICS PARAMETER Access time from CLK (pos. edge) CL = 3 CL = 2 CL = 1 Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CL = 3 CL = 2 CL = 1 CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time CL = 3 CL = 2 CL = 1 Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay Refresh period (4,096 rows) AUTO REFRESH command period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time Auto Precharge Mode Manual Precharge Mode
t t t t t t t t t
-8 SYMBOL
t t t
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 2.5 1 2.5 1 2.5 7 8 19 7 8 22 1 2.5 1.8 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 120,000 ns ns ns 64 100 20 20 1.2 0.5 1 CLK +5ns 15 1.2 ms ns ns ns ns - 7 24 27 10 10 10 23 23 23 NOTES
MIN
AC (3) AC (2) AC (1)
t
AH AS
1 2.5 3 3 8 10 20 1 2.5 1 2.5 1 2.5
t t
CH CL
t
CK (3) CK (2) CK (1)
t
CKH CKS
t t
CMH CMS DH DS
t t
t
HZ (3) HZ (2) HZ (1)
t t
LZ
1 2.5 1.8 48 80 20 64 80 20 20 0.5 1 CLK +7ns 15 120,000
OH
N
tOH
t
RAS
t
50 100 20
RC
RCD REF
t t
RFC RP
t
RRD
t
T
WR (a)
t
WR (m)
ns
25
Exit SELF REFRESH to ACTIVE command
t
XSR
80
100
ns
20
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
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Table 15: AC Functional Characteristics
Notes: 5, 6, 7, 8, 9, 11; notes appear on page 42 PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command CL = 3 CL = 2 CL = 1
t t t
SYMBOL
t t
-8 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2 1
-10 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2 1
UNITS
t t t t t t t t t t t t t t t t
NOTES 17 14 14 17 17 17 17 15, 21 16, 21 17 17 16, 21 26 17 17 17
CCD
CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK
CKED
t
PED
t t
DQD
DQM DQZ
t t
DWD DAL DPL
t t t t
t
BDL CDL RDL
t
MRD
ROH(3) ROH(2) ROH(1)
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Table 16: IDD Specifications and Conditions (x16)
Notes: 1, 3, 6, 11, 13, 31 ; notes appear on page 42; VDD = VDDQ = +3.3V 0.3V or VDD = VDDQ = 2.5V 0.2V or VDD = +2.5V 0.2V, VDDQ = +1.8V 0.15V MAX PARAMETER/CONDITION Operating Current: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) Standby Current: Power-Down Mode; All banks idle; CKE = LOW Standby Current: Active Mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress Operating Current: Burst Mode; Page burst; READ or WRITE; All banks active t Auto Refresh Current RFC = tRFC (MIN) CKE = HIGH; CS# = HIGH t RFC = 15.625s SYMBOL IDD1 IDD2 IDD3 -8 130 350 35 -10 100 350 30 UNITS mA A mA NOTES 18, 19 12, 33 19
IDD4 IDD5 IDD6
100 210 3
95 170 3
mA mA mA
18, 19 12, 18, 19, 32, 33
Table 17: IDD7 Self Refresh Current Options (x16)
(Notes: 4 appears on page 42) VDD = VDDQ = +3.3V 0.3V or VDD = VDDQ = 2.5V 0.2V or VDD = +2.5V 0.2V, VDDQ = +1.8V 0.15V TEMPERATURE COMPENSATED SELF REFRESH PARAMETER/CONDITION Self Refresh Current: CKE < 0.2V MAX TEMPERATURE 85C 70C 45C 15C -8 AND -10 800 500 350 300 UNITS A A A A
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Table 18: IDD Specifications And Conditions (x32)
(Notes: 1, 3, 6, 11, 13, 31 ; notes appear on page 42; VDD = VDDQ = +3.3V 0.3V or VDD = VDDQ = 2.5V 0.2V or VDD = +2.5V 0.2V, VDDQ = +1.8V 0.15V MAX PARAMETER/CONDITION Operating Current: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) Standby Current: Power-Down Mode; All banks idle; CKE = LOW Standby Current: Active Mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress Operating Current: Burst Mode; Page burst; READ or WRITE; All banks active t Auto Refresh Current RFC = tRFC (MIN) CKE = HIGH; CS# = HIGH t RFC = 15.625s SYMBOL IDD1 IDD2 IDD3 -8 150 350 40 -10 120 350 35 UNITS mA A mA NOTES 18, 19 12, 33 19
IDD4 IDD5 IDD6
115 220 3
110 180 3
mA mA mA
18, 19 12, 18, 19, 32, 33
Table 19: IDD7 Self Refresh Current Options (x32)
(Notes: 4 appears on page 42) VDD = VDDQ = +3.3V 0.3V or VDD = VDDQ = 2.5 0.2V or VDD = +2.5V 0.2V, VDDQ = +1.8V 0.15V TEMPERATURE COMPENSATED SELF REFRESH PARAMETER/CONDITION Self Refresh Current: CKE < 0.2V MAX TEMPERATURE 85C 70C 45C 15C -8 AND -10 1000 550 400 350 UNITS A A A A
Table 20: Capacitance
(Note; 2 notes appear on page 42) PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs SYMBOL CI1 CI2 CIO MIN 2.5 2.5 4.0 MAX 3.5 3.8 6.0 UNITS pF pF pF NOTES 28 29 30
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Notes
1. All voltages are referenced to Vss 2. This parameter is sampled. VDD, VDDQ = +3.3V; = 25C; pin under test biased at 1.4V. f = 1 MHz, TA 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full operational temperature range is ensured ( TA = Commercial, IT or XT). 6. An initial pause of 100s is required after powerup, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V (for LC, G devices) or at 1.25V (V devices)with equivalent load: 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 125MHz for -8 and tCK = 100MHz for -10. 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins at 5.4ns for -8 after the first clock delay, after the last WRITE is executed. 25. Precharge mode only. 26. JEDEC and PC100 specify three clocks. 27. Parameter guaranteed by design. 28. PC100 specifies a maximum of 4pF. 29. PC100 specifies a maximum of 5pF. 30. PC100 specifies a maximum of 6.5pF. 31. For -8, CL = 2 and tCK = 10ns; for -10, CL = 3 and t CK =10ns. 32. CKE is HIGH during refresh command period t RFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 33. Specified with I/O's in steady state condition.
Q 30pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet t OH before going High-Z. 11. AC timing and IDD tests use established values for VIL and VIH, with timing referenced to VIH/2 crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL(MAX) and VIH(MIN) and no longer at the VIH/2 crossover point. Established tester values follow: VIL = 0V, VIH = 3.0V for LC devices, VIH = 2.7V for G devices, and VIH = 2.3V for V devices. 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels.
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Figure 33: Initialize and Load Mode Register1,2
T0 CLK
(( )) (( ))
T1
(( )) (( ))
T3
(( )) (( ))
T5
(( )) (( ))
T7
(( )) (( ))
T9
(( )) (( ))
T19
(( )) (( ))
T29
tCK tCKS tCKH
CKE
(( )) (( )) (( )) (( )) (( )) (( ))
tCMS tCMH NOP PRE
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
COMMAND
LMR4
LMR4
PRE3
AR4
AR4
ACT4
DQML, DQMU
tAS tAH A0-A9, A11
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
CODE
(( )) (( )) (( )) (( )) (( )) (( ))
CODE
(( )) (( )) ( ( ALL BANKS )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
RA
ALL BANKS
A10
tAS tAH
(( )) (( )) (( )) (( ))
CODE
CODE
RA
tAS
tAH
BA0 = L, BA1 = L
(( )) (( ))
tAS
tAH
BA
BA0, BA1
BA0 = L, BA1 = H
DQ
High-Z
(( ))
tRP
(( ))
tMRD
(( ))
tMRD
(( ))
tRP
(( ))
(( ))
T = 100s
tRFC tRFC
Power-up: VDD and CLK stable
Load Extended Mode Register
Load Mode Register
DON'T CARE
NOTE:
1. The two AUTO REFRESH commands at T9 and T19 may be applied before either LOAD MODE REGISTER (LMR) command. 2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address 3. Optional refresh command. 4. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order. However, all must occur prior to an Active command. -8 SYMBOL
t 1
-10 MAX MIN 1 2.5 3 3 10 12 25 MAX UNITS ns ns ns ns ns ns ns SYMBOL
t
-8 CKH CKS MIN 1 2.5 1 2.5 2 80 20 MAX MIN 1 2.5 1 2.5 2 100 20
-10 MAX UNITS ns ns ns ns
t
AH AS CL CH
MIN 1 2.5 3 3 8 10 20
t t
t t
CMH CMS RFC RP MRD
t
t t t t
t t
CK (3) CK (2) CK (1)
t
CK ns
ns
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
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Figure 34: Power-down Mode1
T0 CLK tCK T1 tCL tCKS CKE tCKS tCKH tCH T2
(( )) (( ))
Tn + 1
Tn + 2
tCKS
(( ))
tCMS tCMH COMMAND
PRECHARGE NOP NOP
(( )) (( )) (( )) (( )) (( )) (( ))
NOP
ACTIVE
DQML, DQMU
A0-A9, A11
ALL BANKS
ROW
A10
SINGLE BANK
(( )) (( ))
ROW
tAS BA0, BA1
tAH
(( )) (( ))
(( ))
BANK(S)
High-Z
BANK
DQ Two clock cycles Precharge all active banks All banks idle, enter power-down mode
Input buffers gated off while in power-down mode All banks idle Exit power-down mode DON'T CARE
NOTE:
1. Violating refresh requirements during power-down may result in a loss of data. -8 SYMBOL
t 1
-10 MAX MIN 1 2.5 3 3 10 12 25 MAX UNITS ns ns ns ns ns ns ns SYMBOL*
t
-8 CKH CKS MIN 1 2.5 1 2.5 2 80 20 MAX MIN 1 2.5 1 2.5 2 100 20
-10 MAX UNITS ns ns ns ns
t
AH AS CL CH
MIN 1 2.5 3 3 8 10 20
t t
t t
CMH CMS RFC RP MRD
t
t t t t
t t
CK (3) CK (2) CK (1)
t
CK ns
ns
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
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128Mb: x16, x32 MOBILE SDRAM
Figure 35: Clock Suspend Mode
T0
CLK tCK
T1
tCL
T2
tCH tCKS tCKH
T3
T4
T5
T6
T7
T8
T9
CKE tCKS tCKH
tCMS tCMH COMMAND
READ NOP NOP NOP NOP NOP WRITE NOP
tCMS tCMH DQMU, DQML tAS A0-A9, A11 tAH
COLUMN e 2
COLUMN m 2
tAS A10 tAS BA0, BA1
tAH
tAH
BANK BANK
tAC tAC DQ tLZ
DOUT m
tOH
tHZ
DOUT m + 1
tDS
tDH
DOUT e + 1
DOUT e
UNDEFINED
DON'T CARE
NOTE:
1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled. 2. x16:A9 and A11 = "Don't Care" x32:A8, A9 and A11 = "Don't Care"
-8 SYMBOL
t t t 1
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 UNITS ns ns ns ns ns ns ns ns ns ns
t t t
-8 SYMBOL*
t
-10 MAX MIN 1 2.5 1 2.5 1 2.5 7 8 19 7 8 22 1 2.5 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns
MIN
AC (3) AC (2) AC (1)
t
CKH CKS
MIN 1 2.5 1 2.5 1 2.5
t t
CMH CMS
t
AH AS CL CH
1 2.5 3 3 8 10 20
t
t t
DH DS
t
t t t t
HZ (3) HZ (2) HZ (1)
t t
CK (3) CK (2) CK (1)
LZ
1 2.5
OH
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 36: Auto Refresh Mode
T0
CLK tCK
T1
T2
tCH
(( )) (( )) (( ))
Tn + 1
tCL
(( )) (( )) (( ))
To + 1
CKE tCKS tCMS COMMAND tCKH tCMH
NOP AUTO REFRESH NOP
PRECHARGE
(( )) ( ( NOP )) (( )) (( ))
(( )) (( ))
AUTO REFRESH
NOP
(( )) ( ( NOP )) (( )) (( ))
(( )) (( )) (( )) (( ))
ACTIVE
DQMU, DQML
A0-A9, A11
ALL BANKS
ROW
A10
SINGLE BANK tAS BA0, BA1 tAH
(( )) (( ))
ROW
BANK(S)
(( )) (( )) (( )) tRP tRFC1 tRFC1
(( )) (( )) (( ))
BANK
DQ
High-Z
Precharge all active banks
DON'T CARE
NOTE:
1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.
.
-8 SYMBOL1
t
-10 MAX MIN 1 2.5 3 3 10 12 25 MAX UNITS ns ns ns ns ns ns ns SYMBOL
t
-8 CKH CKS MIN 1 2.5 1 2.5 2 80 20 MAX MIN 1 2.5 1 2.5 2 100 20
-10 MAX UNITS ns ns ns ns
t
AH AS CL CH
MIN 1 2.5 3 3 8 10 20
t t
t t
CMH CMS RFC RP MRD
t
t t t t
t t
CK (3) CK (2) CK (1)
t
CK ns
ns
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
46
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 37: Self Refresh Mode
T0
CLK tCK
T1
tCH
tCL
T2
tCKS
> tRAS1
(( ))
(( )) (( ))
Tn + 1
(( )) (( )) (( )) (( ))
To + 1
To + 2
CKE tCKS tCMS COMMAND tCKH tCMH
NOP AUTO REFRESH
PRECHARGE
(( )) (( )) (( )) (( )) (( )) (( ))
NOP ( (
(( ))
AUTO REFRESH
))
DQMU, DQML
(( )) (( )) (( )) (( )) (( )) (( ))
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
(( )) (( ))
t AS BA0, BA1
tAH
(( )) (( )) (( )) (( ))
BANK(S)
DQ
High-Z tRP Precharge all active banks
(( ))
(( ))
tXSR2 Enter self refresh mode Exit self refresh mode (Restart refresh time base)
DON'T CARE
CLK stable prior to exiting self refresh mode
NOTE:
1. No maximum time limit for Self Refresh. tRAS (MAX) only applies to non-Self Refresh mode. 2. tXSR requires a minimum of two clocks regardless of frequency or timing. 3. As a general rule, any time Self Refresh is exited, the DRAM may not re-enter the Self Refresh Mode until all rows have been refreshed via the Auto Refresh command at the distributed refresh rate, tREF, or faster. However, the following exception is allowed. Self Refresh Mode may be re-entered any time after exiting, if the following conditions are all met: a.) The DRAM has been in the Self Refresh Mode for a minimum of 64ms prior to exiting. b.) tXSR has not been violated. c.) At least two Auto Refresh commands are performed during each 15.625us interval while the DRAM remains out of the Self Refresh mode. -8 SYMBOL
t
-10 MAX MIN 1 2.5 3 3 10 12 25 MAX UNITS ns ns ns ns ns ns ns SYMBOL
t
-8 CKH CKS MIN 1 2.5 1 2.5 48 20 80 120,000 MAX MIN 1 2.5 1 2.5 50 20 100
-10 MAX UNITS ns ns ns ns 120,000 ns ns ns
AH AS CL CH
MIN 1 2.5 3 3 8 10 20
t t
t t
CMH CMS RAS
t
t t t t
t
CK (3) CK (2) CK (1)
t
RP
t
XSR
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
47
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 38: READ - Without Auto Precharge1
T0
CLK tCKS CKE tCMS tCMH COMMAND ACTIVE NOP READ tCMS tCMH DQMU, DQML tAS A0-A9, A11 tAS A10 tAS BA0, BA1 tAH ROW tAH ROW tAH BANK DISABLE AUTO PRECHARGE BANK tAC tAC DQ tRCD tRAS tRC tLZ CAS Latency tOH tAC tOH DOUT m+1 SINGLE BANKS BANK(S) tAC tOH DOUT m+2 tRP tOH DOUT m+3 tHZ BANK
COLUMN m2
T1
tCK tCKH tCL
T2
tCH
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
ROW ALL BANKS ROW
DOUT m
DON'T CARE UNDEFINED
NOTE:
1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. x16:A9 and A11 = "Don't Care" x32:A8, A9,and A11 = "Don't Care" -8 SYMBOL
t t t 1
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 2.5 1 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
t t t t t
-8 SYMBOL
t t
-10 MAX MIN 2.5 1 2.5 7 8 19 7 8 22 1 2.5 MAX UNITS ns ns ns ns ns ns ns ns 120,000 ns ns ns ns
MIN
AC (3) AC (2) AC (1)
t
CKS
MIN 2.5 1 2.5
CMH CMS
t
AH AS CL CH
1 2.5 3 3 8 10 20 1 2.5 1
HZ (3) HZ (2) HZ (1)
t t
t t
t t t t
LZ
1 2.5 48 80 20 20 120,000
CK (3) CK (2) CK (1)
t
OH RC RP
RAS
50 100 20 20
t
CKH CKS
RCD
t
t t
CMH
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
48
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 39: Read - With Auto Precharge1
T0
CLK tCKS CKE tCMS tCMH COMMAND
ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE
T1
tCK tCKH tCL
T2
tCH
T3
T4
T5
T6
T7
T8
tCMS DQMU, DQML tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m 2
ROW
tAS A10
tAH
ENABLE AUTO PRECHARGE ROW
ROW
tAS BA0, BA1
tAH
BANK BANK
BANK
tAC DQ tRCD tRAS tRC tLZ CAS Latency
tAC tOH
DOUT m
tAC tOH
DOUT m + 1
tAC tOH
DOUT m + 2
tOH
DOUT m + 3
tHZ tRP
DON'T CARE UNDEFINED
NOTE:
1. For this example, the burst length = 4, the CAS latency = 2. 2. x16:A9 and A11 = "Don't Care" x32:A8, A9,and A11 = "Don't Care" -8 SYMBOL
t t t 1
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 2.5 1 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
t t t t t
-8 SYMBOL
t t
-10 MAX MIN 2.5 1 2.5 7 8 19 7 8 22 1 2.5 MAX UNITS ns ns ns ns ns ns ns ns 120,000 ns ns ns ns
MIN
AC (3) AC (2) AC (1)
t
CKS
MIN 2.5 1 2.5
CMH CMS
t
AH AS CL CH
1 2.5 3 3 8 10 20 1 2.5 1
HZ (3) HZ (2) HZ (1)
t t
t t
t t t t
LZ
1 2.5 48 80 20 20 120,000
CK (3) CK (2) CK (1)
t
OH RC RP
RAS
50 100 20 20
t
CKH CKS
RCD
t
t t
CMH
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
49
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 40: Single Read - Without Auto Precharge1
T0
CLK tCKS CKE tCMS tCMH COMMAND ACTIVE NOP READ tCMS tCMH DQMU, DQML tAS A0-A9, A11 tAS A10 tAS BA0, BA1 tAH ROW tAH ROW tAH BANK DISABLE AUTO PRECHARGE BANK SINGLE BANKS BANK(S) BANK
COLUMN m2
T1
tCK tCKH tCL
T2
tCH
T3
T4
T5
T6
T7
T8
NOP 3
NOP 3
PRECHARGE
NOP
ACTIVE
NOP
ROW ALL BANKS ROW
tAC DQ tRCD tRAS tRC tLZ CAS Latency
tOH
DOUT m
tHZ tRP
UNDEFINED
DON'T CARE
NOTE:
1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. x16:A9 and A11 = "Don't Care" x32:A8, A9,and A11 = "Don't Care" 3. PRECHARGE command not allowed or tRAS would be violated. -8 SYMBOL1
t t t
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 2.5 1 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
t t t t t
-8 SYMBOL
t t
-10 MAX MIN 2.5 1 2.5 7 8 19 7 8 22 1 2.5 MAX UNITS ns ns ns ns ns ns ns ns 120,000 ns ns ns ns
MIN
AC (3) AC (2) AC (1)
t
CKS
MIN 2.5 1 2.5
CMH CMS
t
AH AS CL CH
1 2.5 3 3 8 10 20 1 2.5 1
HZ (3) HZ (2) HZ (1)
t t
t t
t t t t
LZ
1 2.5 48 80 20 20 120,000
CK (3) CK (2) CK (1)
t
OH RC RP
RAS
50 100 20 20
t
CKH CKS
RCD
t
t t
CMH
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
50
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 41: Single Read - With Auto Precharge1
T0
CLK tCKS CKE tCMS tCMH COMMAND
ACTIVE NOP NOP3 NOP3 READ NOP NOP ACTIVE NOP
T1
tCK tCKH tCL
T2
tCH
T3
T4
T5
T6
T7
T8
tCMS DQMU, DQML tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m2
ROW
tAS A10
tAH
ENABLE AUTO PRECHARGE ROW
ROW
tAS BA0, BA1
tAH
BANK BANK
BANK
tAC t OH DQ tRCD tRAS tRC CAS Latency tRP
DOUT m
tHZ
UNDEFINED
DON'T CARE
NOTE:
1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. x16:A9 and A11 = "Don't Care" x32:A8, A9,and A11 = "Don't Care" 3. PRECHARGE command not allowed or tRAS would be violated. -8 SYMBOL
t t t 1
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 2.5 1 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
t t t t t
-8 SYMBOL
t t
-10 MAX MIN 2.5 1 2.5 7 8 19 7 8 22 1 2.5 MAX UNITS ns ns ns ns ns ns ns ns 120,000 ns ns ns ns
MIN
AC (3) AC (2) AC (1)
t
CKS
MIN 2.5 1 2.5
CMH CMS
t
AH AS CL CH
1 2.5 3 3 8 10 20 1 2.5 1
HZ (3) HZ (2) HZ (1)
t t
t t
t t t t
LZ
1 2.5 48 80 20 20 120,000
CK (3) CK (2) CK (1)
t
OH RC RP
RAS
50 100 20 20
t
CKH CKS
RCD
t
t t
CMH
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
51
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 42: Alternating Bank Read Accesses1
T0
CLK tCKS CKE tCMS COMMAND tCMH
NOP READ NOP ACTIVE NOP READ NOP ACTIVE
T1
tCK tCKH tCL
T2
tCH
T3
T4
T5
T6
T7
T8
ACTIVE
tCMS DQMU, DQML tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m 2
ROW
COLUMN b 2
ROW
tAS A10
tAH
ENABLE AUTO PRECHARGE ROW
ENABLE AUTO PRECHARGE ROW
ROW
tAS BA0, BA1
tAH
BANK 0 BANK 3 BANK 3 BANK 0
BANK 0
tAC DQ tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRRD tLZ CAS Latency - BANK 0
tAC tOH
DOUT m
tAC tOH
DOUT m + 1
tAC tOH
DOUT m + 2
tAC tOH
DOUT m + 3
tAC tOH
DOUT b
tRP - BANK 0
tRCD - BANK 0
tRCD - BANK 3
CAS Latency - BANK 3 UNDEFINED DON'T CARE
NOTE:
1. For this example, the burst length = 4, the CAS latency = 2. 2. x16:A9 and A11 = "Don't Care" x32:A8, A9,and A11 = "Don't Care." -8 SYMBOL1
t t t
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 2.5 1 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
t t t t t t
-8 SYMBOL
t t
-10 MAX MIN 2.5 1 2.5 7 8 19 7 8 22 1 2.5 MAX UNITS ns ns ns ns ns ns ns ns 120,000 ns ns ns ns ns
MIN
AC (3) AC (2) AC (1)
t
CKS
MIN 2.5 1 2.5
CMH CMS
t
AH AS CL CH
1 2.5 3 3 8 10 20 1 2.5 1
HZ (3) HZ (2) HZ (1)
t t
t t
t t t t
LZ
1 2.5 48 80 20 20 20 120,000
CK (3) CK (2) CK (1)
t
OH RC RP
RAS
50 100 20 20 20
t
CKH CKS
RCD
t
t t
CMH
RRD
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
52
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 43: Read - Full-page Burst1
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP READ NOP NOP NOP NOP
T1 tCK tCKH
tCL
T2 tCH
T3
T4
T5
T6
(( )) (( ))
Tn + 1
Tn + 2
Tn + 3
Tn + 4
(( )) (( )) (( )) (( )) (( )) (( ))
ACTIVE
NOP
BURST TERM
NOP
NOP
tCMS DQMU, DQML
tCMH
tAS A0-A9, A11
tAH
COLUMN m 2
ROW
(( )) (( ))
tAS A10
tAH
ROW
(( )) (( ))
tAS BA0, BA1
tAH
BANK
BANK
(( )) (( ))
tAC tAC DQ tLZ tRCD CAS Latency tOH
DOUT m
tAC tOH
DOUT m+1
tAC ( ( tOH ) )
(( )) DOUT m+2 (( ))
tAC tOH
DOUT m-1
tAC tOH
DOUT m
tOH
DOUT m+1
512 (x16) locations within same row
tHZ
Full page completed
UNDEFINED DON'T CARE
Full-page burst does not self-terminate. 3 Can use BURST TERMINATE command.
NOTE:
1. For this example, the CAS latency = 2. 2. x16:A9 and A11 = "Don't Care" x32:A8, A9,and A11 = "Don't Care" 3. Page left open; no tRP. -8 SYMBOL
t t t 1
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 2.5 1 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
t t t t t t
-8 SYMBOL
t t
-10 MAX MIN 2.5 1 2.5 7 8 19 7 8 22 1 2.5 MAX UNITS ns ns ns ns ns ns ns ns 120,000 ns ns ns ns ns
MIN
AC (3) AC (2) AC (1)
t
CKS
MIN 2.5 1 2.5
CMH CMS
t
AH AS CL CH
1 2.5 3 3 8 10 20 1 2.5 1
HZ (3) HZ (2) HZ (1)
t t
t t
t t t t
LZ
1 2.5 48 80 20 20 20 120,000
CK (3) CK (2) CK (1)
t
OH RC RP
RAS
50 100 20 20 20
t
CKH CKS
RCD
t
t t
CMH
RRD
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
53
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 44: Read - DQM Operation1
T0
CLK tCKS CKE tCMS COMMAND tCMH
NOP READ NOP NOP NOP NOP NOP NOP
T1
tCK tCKH tCL
T2
tCH
T3
T4
T5
T6
T7
T8
ACTIVE
tCMS DQMU, DQML tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m 2 ENABLE AUTO PRECHARGE
tAS A10
tAH
ROW
tAS BA0, BA1
tAH
BANK
DISABLE AUTO PRECHARGE BANK
tAC DQ tLZ tRCD CAS Latency
tOH
DOUT m
tAC
tAC tOH
DOUT m + 2
tOH
DOUT m + 3
tHZ
tLZ
tHZ UNDEFINED DON'T CARE
NOTE:
1. For this example, the CAS latency = 2. 2. x16:A9 and A11 = "Don't Care" x32:A8, A9,and A11 = "Don't Care" -8 SYMBOL
t t t 1
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 2.5 1 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
t t t t t t
-8 SYMBOL
t t
-10 MAX MIN 2.5 1 2.5 7 8 19 7 8 22 1 2.5 MAX UNITS ns ns ns ns ns ns ns ns 120,000 ns ns ns ns ns
MIN
AC (3) AC (2) AC (1)
t
CKS
MIN 2.5 1 2.5
CMH CMS
t
AH AS CL CH
1 2.5 3 3 8 10 20 1 2.5 1
HZ (3) HZ (2) HZ (1)
t t
t t
t t t t
LZ
1 2.5 48 80 20 20 20 120,000
CK (3) CK (2) CK (1)
t
OH RC RP
RAS
50 100 20 20 20
t
CKH CKS
RCD
t
t t
CMH
RRD
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
54
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 45: Write - Without Auto Precharge1
T0
CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP NOP NOP NOP PRECHARGE NOP ACTIVE
T1
tCK tCKH
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
T9
ACTIVE
tCMS tCMH DQMU, DQML tAS A0-A9, A11 tAH
COLUMN m 3 ALL BANKS ROW DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK ROW
ROW
tAS A10
tAH
ROW
tAS BA0, BA1
tAH
BANK
tDS DQ tRCD tRAS tRC
tDH
tDS
tDH
tDS
tDH
tDS
tDH
DIN m
DIN m + 1
DIN m + 2
DIN m + 3
t WR 2 tRP
UNDEFINED
DON'T CARE
NOTE:
1. For this example, the burst length = 4, and the WRITE burst is followed by a "manual" PRECHARGE. 2. 15ns is required between and the PRECHARGE command, regardless of frequency. 3. x16: A9 and A11 = "Don't Care" x32: A8, A9,and A11 = "Don't Care" -8 SYMBOL1
t t t
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 UNITS ns ns ns ns ns ns ns ns ns ns ns
t t t
-8 SYMBOL
t t
-10 MAX MIN 2.5 1 2.5 1 2.5 MAX UNITS ns ns ns ns ns 120,000 ns ns ns ns - ns
MIN
AC (3) AC (2) AC (1)
t
CKS
MIN 2.5 1 2.5 1 2.5 48 80 20 20 1 CLK +7ns 15
CMH CMS
t
t
AH AS CL CH
1 2.5 3 3 8 10 20 1
DH DS RC RP
t t
t t
RAS
120,000
50 100 20 20 1 CLK +5ns 15
t t t t
t
CK (3) CK (2) CK (1)
t
RCD
t
WR (a)
CKH
WR (m)
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
55
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 46: Write - With Auto Precharge1
T0
CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP NOP NOP NOP NOP NOP ACTIVE
T1
tCK tCKH
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
T9
ACTIVE
tCMS tCMH DQMU, DQML tAS A0-A9, A11 tAH
COLUMN m 2 ENABLE AUTO PRECHARGE ROW ROW
ROW
tAS A10
tAH
ROW
tAS BA0, BA1
tAH
BANK BANK
BANK
tDS DQ tRCD tRAS tRC
tDH
tDS
tDH
tDS
tDH
tDS
tDH
DIN m
DIN m + 1
DIN m + 2
DIN m + 3
tWR tRP
DON'T CARE
NOTE:
1. For this example, the burst length = 4. 2. x16: A9 and A11 = "Don't Care" x32: A8, A9,and A11 = "Don't Care" -8 SYMBOL1
t t t
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 UNITS ns ns ns ns ns ns ns ns ns ns ns
t t t
-8 SYMBOL
t t
-10 MAX MIN 2.5 1 2.5 1 2.5 MAX UNITS ns ns ns ns ns 120,000 ns ns ns ns - ns
MIN
AC (3) AC (2) AC (1)
t
CKS
MIN 2.5 1 2.5 1 2.5 48 80 20 20 1 CLK +7ns 15
CMH CMS
t
t
AH AS CL CH
1 2.5 3 3 8 10 20 1
DH DS RC RP
t t
t t
RAS
120,000
50 100 20 20 1 CLK +5ns 15
t t t t
t
CK (3) CK (2) CK (1)
t
RCD
t
WR (a)
CKH
WR (m)
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
56
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 47: Single Write - Without Auto Precharge1
T0
CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP 4 NOP 4 PRECHARGE NOP ACTIVE NOP
T1
tCK tCKH
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
ACTIVE
tCMS tCMH DQMU, DQML tAS A0-A9, A11 tAH
COLUMN m 3 ALL BANKS ROW DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK
ROW
tAS A10
tAH
ROW
tAS BA0, BA1
tAH
BANK
tDS DQ tRCD tRAS tRC
tDH
DIN m
t WR 2 tRP
DON'T CARE
NOTE:
1. For this example, the burst length = 1, and the WRITE burst is followed by a "manual" PRECHARGE. 2. 15ns is required between and the PRECHARGE command, regardless of frequency. 3. x16:A9 and A11 = "Don't Care" x32:A8, A9,and A11 = "Don't Care" 4. PRECHARGE command not allowed else tRAS would be violated. -8 SYMBOL
t t t 1
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 UNITS ns ns ns ns ns ns ns ns ns ns ns
t t t
-8 SYMBOL
t t
-10 MAX MIN 2.5 1 2.5 1 2.5 MAX UNITS ns ns ns ns ns 120,000 ns ns ns ns - ns
MIN
AC (3) AC (2) AC (1)
t
CKS
MIN 2.5 1 2.5 1 2.5 48 80 20 20 1 CLK +7ns 15
CMH CMS
t
t
AH AS CL CH
1 2.5 3 3 8 10 20 1
DH DS RC RP
t t
t t
RAS
120,000
50 100 20 20 1 CLK +5ns 15
t t t t
t
CK (3) CK (2) CK (1)
t
RCD
t
WR (a)
CKH
WR (m)
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
57
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 48: Single Write - With Auto Precharge1
T0
CLK tCKS CKE tCMS COMMAND tCMH
NOP3 NOP3 NOP3 WRITE NOP NOP NOP ACTIVE NOP
T1
tCK tCKH
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
T9
ACTIVE
tCMS DQMU, DQML tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m 2 ENABLE AUTO PRECHARGE
ROW
tAS A10
tAH
ROW
ROW
tAS BA0, BA1
tAH
BANK BANK
BANK
tDS DQ tRCD tRAS tRC
tDH
DIN m
tWR tRP
DON'T CARE
NOTE:
1. For this example, the burst length = 1, and the WRITE burst is followed by a "manual" PRECHARGE. 2. 15ns is required between and the PRECHARGE command, regardless of frequency. 3. x16:A9 and A11 = "Don't Care" x32:A8, A9,and A11 = "Don't Care" 4. WRITE command not allowed else tRAS would be violated. -8 SYMBOL
t t t 1
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 UNITS ns ns ns ns ns ns ns ns ns ns ns
t t t
-8 SYMBOL
t t
-10 MAX MIN 2.5 1 2.5 1 2.5 MAX UNITS ns ns ns ns ns 120,000 ns ns ns ns - ns
MIN
AC (3) AC (2) AC (1)
t
CKS
MIN 2.5 1 2.5 1 2.5 48 80 20 20 1 CLK +7ns 15
CMH CMS
t
t
AH AS CL CH
1 2.5 3 3 8 10 20 1
DH DS RC RP
t t
t t
RAS
120,000
50 100 20 20 1 CLK +5ns 15
t t t t
t
CK (3) CK (2) CK (1)
t
RCD
t
WR (a)
CKH
WR (m)
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
58
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 49: Alternating Bank Write Accesses1
T0
CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE
T1
tCK tCKH
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
T9
ACTIVE
tCMS DQMU, DQML tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m 2
ROW
COLUMN b 2
ROW
tAS A10
tAH
ENABLE AUTO PRECHARGE ROW
ENABLE AUTO PRECHARGE ROW
ROW
tAS BA0, BA1
tAH
BANK 0 BANK 1 BANK 1 BANK 0
BANK 0
tDS DQ tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRRD
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
DIN m
DIN m + 1
DIN m + 2
DIN m + 3
DIN b
tWR - BANK 0
DIN b + 1
tRP - BANK 0
DIN b + 2
DIN b + 3
tRCD - BANK 0
tRCD - BANK 1
tWR - BANK 1
DON'T CARE
NOTE:
1. For this example, the burst length = 4. 2. x16: A9 and A11 = "Don't Care" x32: A8, A9,and A11 = "Don't Care" -8 SYMBOL1
t t t
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 UNITS ns ns ns ns ns ns ns ns ns ns ns
t t t
-8 SYMBOL
t t
-10 MAX MIN 2.5 1 2.5 1 2.5 MAX UNITS ns ns ns ns ns 120,000 ns ns ns ns - ns
MIN
AC (3) AC (2) AC (1)
t
CKS
MIN 2.5 1 2.5 1 2.5 48 80 20 20 1 CLK +7ns 15
CMH CMS
t
t
AH AS CL CH
1 2.5 3 3 8 10 20 1
DH DS RC RP
t t
t t
RAS
120,000
50 100 20 20 1 CLK +5ns 15
t t t t
t
CK (3) CK (2) CK (1)
t
RCD
t
WR (a)
CKH
WR (m)
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
59
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 50: Write - Full-page Burst1
T0
CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP NOP NOP
T1
tCK tCKH
tCL
T2
tCH
T3
T4
T5
(( )) (( ))
Tn + 1
Tn + 2
Tn + 3
(( )) (( )) (( )) (( ))
ACTIVE
NOP
BURST TERM
NOP
tCMS tCMH DQMU, DQML
(( )) (( ))
tAS A0-A9, A11
tAH
COLUMN m 1
ROW
(( )) (( ))
tAS A10
tAH
ROW
(( )) (( ))
tAS BA0, BA1
tAH
BANK
BANK
(( )) (( ))
tDS DQ tRCD
tDH
tDS
tDH
tDS
tDH
tDS
tDH
DIN m
DIN m + 1
DIN m + 2
DIN m + 3
(( )) (( ))
tDS
tDH
DIN m - 1
Full-page burst does not self-terminate. Can use BURST TERMINATE command to stop.2, 3
512 (x16) locations within same row DON'T CARE
Full page completed
NOTE:
1. x16: A9 and A11 = "Don't Care" x32: A8, A9,and A11 = "Don't Care" 2. tWR must be satisfied prior to PRECHARGE command. 3. Page left open; no tRP. -8 SYMBOL
t t t 1
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 UNITS ns ns ns ns ns ns ns ns ns ns ns
t t t
-8 SYMBOL
t t
-10 MAX MIN 2.5 1 2.5 1 2.5 MAX UNITS ns ns ns ns ns 120,000 ns ns ns ns - ns
MIN
AC (3) AC (2) AC (1)
t
CKS
MIN 2.5 1 2.5 1 2.5 48 80 20 20 1 CLK +7ns 15
CMH CMS
t
t
AH AS CL CH
1 2.5 3 3 8 10 20 1
DH DS RC RP
t t
t t
RAS
120,000
50 100 20 20 1 CLK +5ns 15
t t t t
t
CK (3) CK (2) CK (1)
t
RCD
t
WR (a)
CKH
WR (m)
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
60
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 51: Write - DQM Operation1
T0
CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP NOP NOP NOP NOP
T1
tCK tCKH
tCL
T2
tCH
T3
T4
T5
T6
T7
ACTIVE
tCMS tCMH DQMU, DQML tAS A0-A9, A11 tAH
COLUMN m 2 ENABLE AUTO PRECHARGE
ROW
tAS A10
tAH
ROW
tAS BA0, BA1
tAH
DISABLE AUTO PRECHARGE BANK
BANK
tDS DQ tRCD
tDH
DIN m
tDS
tDH
tDS
tDH
DIN m + 2
DIN m + 3
DON'T CARE
NOTE:
1. For this example, the burst length = 4. 2. x16: A9 and A11 = "Don't Care" x32: A8, A9,and A11 = "Don't Care." -8 SYMBOL1
t t t
-10 MAX 7 8 19 MIN MAX 7 8 22 1 2.5 3 3 10 12 25 1 UNITS ns ns ns ns ns ns ns ns ns ns ns
t t t
-8 SYMBOL
t t
-10 MAX MIN 2.5 1 2.5 1 2.5 MAX UNITS ns ns ns ns ns 120,000 ns ns ns ns - ns
MIN
AC (3) AC (2) AC (1)
t
CKS
MIN 2.5 1 2.5 1 2.5 48 80 20 20 1 CLK +7ns 15
CMH CMS
t
t
AH AS CL CH
1 2.5 3 3 8 10 20 1
DH DS RC RP
t t
t t
RAS
120,000
50 100 20 20 1 CLK +5ns 15
t t t t
t
CK (3) CK (2) CK (1)
t
RCD
t
WR (a)
CKH
WR (m)
NOTE:
1. CAS latency indicated in parentheses.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
61
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 52: 54-Ball FBGA (8mm x 9mm)
0.70 0.075
SEATING PLANE C 0.1 C
54X 0.35 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS O 0.33 BALL A9
6.40 0.80 TYP
BALL A1 ID BALL A1
0.80 TYP
1.1 MAX
BALL A1 ID
6.40 C L 3.20 0.05
9.00 0.10
4.50 0.05
C L 3.20 0.05 4.00 0.05 8.00 0.10
MOLD COMPOUND: EPOXY NOVOLAC SUBSTRATE: PLASTIC LAMINATE SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3%Ag, 0.5% Cu SOLDER BALL PAD: O .27mm
NOTE:
1. All dimensions in millimeters.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
62
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 53: 54-Ball VFBGA (8mm x 8mm)
0.65 0.05
SEATING PLANE C 0.10 C SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3%Ag, 0.5% Cu SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC BALL A1 ID BALL A1 ID
54X O0.45 0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS 0.42. BALL A9
6.40 0.80 TYP
BALL A1 4.00 0.05 C L 8.00 0.10
6.40
3.20 0.05
0.80 TYP
C L 3.20 0.05 4.00 0.05 1.00 MAX
8.00 0.10
NOTE:
1. All dimensions in millimeters.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
63
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 54: 90-Ball FBGA (11mm x 13mm)
.850 .075 .10 C
SEATING PLANE
C
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3%Ag, 0.5% Cu SOLDER BALL PAD: O .33mm 11.00 .10 90X O 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS O 0.40mm 6.40 .80 TYP
BALL A1 ID
SUBSTRATE: PLASTIC LAMINATE ENCAPSULATION MATERIAL: EPOXY NOVOLAC
BALL A1 ID
BALL A9 6.50 .05
BALL A1 13.00 .10 C L 11.20
5.60 .05
.80 TYP
C L 3.20 .05 1.20 MAX 5.50 .05
NOTE:
1. All dimensions in millimeters. 2. Recommended pad size for PCB is 0.33mm0.025mm.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN
64
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Figure 55: 90-Ball VFBGA (8mm x 13mm)
0.65 0.05
SEATING PLANE C
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3%Ag, 0.5% Cu SOLDER MASK DEFINED BALL PADS: O0.40
0.10 C
90X O0.45 0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS O0.42 BALL A9
6.40 0.80 TYP
SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC
BALL A1 ID
BALL A1 ID BALL A1
0.80 TYP 11.20 0.10 C L 13.00 0.10
5.60 0.05 6.50 0.05
C L 3.20 0.05 4.00 0.05 1.00 MAX
8.00 0.10
NOTE:
1. All dimensions in millimeters. 2. Recommended pad size for PCB is 0.4mm0.025mm.
(R)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.
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